View CXA2161R_24152.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXA2161R
I2C Bus Compatible Audio Video (AV) Switch & Electronic Volume Control
Description The Sony CXA2161R is an Audio/Video switch designed primarily for application in Digital Set Top Boxes. It provides video and audio routing from the digital encoder source to the TV and VCR scart (peritelevision) connectors. In addition, the TV audio output has a programmable volume control. The chip is programmed by means of an I2C interface and can operate from a single or dual power supply. Target specifications: Canal+, BSkyB, TPS, NorDig, and ECCA Euro-Box Features Supply * Single: 0V, +5V, +12V * Dual: 0V, -5V, +5V and +12V (Low number of external parts required) Video * 2 scart switching (VCR, TV) * VCR input supports RGB mode * Integrated 75 drivers for direct video connection * Y/C mixer with trap for RF modulators * Switchable clamps on inputs * Adjustable gain on RGB outputs * Video output shutdown for low power modes * Fast blanking switch * Slow blanking switch for TV and VCR output * SVHS switch on VCR output * Y/C auxiliary input Audio * Four stereo audio inputs * Volume control (-56dB to +6dB in 2dB steps) * Additional switchable gain on audio DAC inputs * Audio overlay facility * Volume bypass for TV and Phono outputs * Mono switching on TV, VCR outputs * High drive capability (600 loads possible) * Switchable audio limiter function * Switchable Mono output for RF modulators * Audio output disable 56 pin LQFP (Plastic)
I2C and Logic * Fast mode compatible I2C bus * Function monitor with loop through * Interrupt output for function monitor * Logic output pin * Sync detector for Y/CVBS inputs Applications * Digital Set Top Box * Integrated digital television Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25C) unless stated * Supply voltage VCC 14 V * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1.1 W (when mounted on the board) Operating Conditions * Single supply * Dual supply
* Operating temperature
Topr
12 0.6 5 0.25 -5 0.25 5 0.25 12 0.6 -20 to +75
V V V V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E00202-PS
CXA2161R
Block Diagram (1) Video and Digital Section
Typical Connection FBLK_SW +3.5V 0V DIG VCR FBLK_IN1 10 FBLK_IN2 12 VIDEO SWITCH1 (TV) DIG BLUE VCR BLUE VIN_1 50 VIN_2 7 DC Restore DC Restore x2 Output disable 47 9 TV_FBLK
Typical Connection
VOUT_1 TV BLUE
DIG GREEN/CVBS VCR GREEN
VIN_3 51 VIN_4 6
DC Restore/Tip DC Restore x2 Output disable 46 VOUT_2 TV GREEN TV
DIG RED/CHROMA DIG CHROMA VCR RED/CHROMA AUX CHROMA
VIN_5 52 VIN_6 53 VIN_7 VIN_13 5 1
DC Restore/C bias C bias DC Restore/C bias C bias Clamp Cntl RGB Gain Control (+1, 2, 3dB) x2 Output disable 45 VOUT_3 TV RED/C
DIG CVBS/LUMA DIG CVBS/LUMA VCR CVBS/LUMA TV CVBS AUX Y/CVBS
VIN_8 54 VIN_9 55 VIN_10 VIN_11 4 3
Tip Tip Tip Tip Tip x2 Output disable 43 VOUT_4 TV CVBS/Y
VIN_12 56
MIX_SW SYNC_ID 2 Sync Detect Output disable & Bi-drection Control
x2
41
VOUT_5 VCR CHROMA
AUD_BIAS 18 VID_BIAS 49 +5V/12V_VCCA 24 -5V_GNDA 21 +5V_DIG 14 GND_DIG 8 x2
VCR
Output disable
39 VOUT_6 VCR CVBS/Y
+5V_VOUT 44 GND_VID 40 +5V_VID 48 +12V_DIG 15 Bias Mute x2 VIDEO SWITCH2 (VCR) MIX_SW SDA 34 0/6/12V SCL 35 VCR FNC_VCR 13 11 FNC_TV TV 38 VOUT_7 (CVBS) RF MOD 37 TRAP
0/6/12V Monitor 3.3V or 5V Fast Mode Compatible Interrupt Control Logic 36 INTRUPT MICRO 33 LOGIC
Note) All video outputs contain 75 drivers, except VOUT_7 (Pin 38). -2-
(2) Audio section
Mono Switch
6dB
32
MONO To RF Modulator
Vol Bypass (Phono)
6dB
31 PHONO_R
Overlay on/off AUDIO SWITCH1 (TV) -16dB Limiter 2.2Vrms 2dB Overlay on/off ZCD -16dB Limiter 2.2Vrms 2dB Vol Bypass (TV) Volume Control +6 to -56dB Vol Bypass (Phono) Tone mix AUDIO SWITCH2 (VCR) Mono and R/L Switch Vol Bypass (TV)
RIN_1 (DIG)
23
-6/-3/0/+3dB
RIN_2 (VCR)
20
-6dB
6dB
26 RTV
RIN_3 (TV/OVERLAY)
17
-6/-11dB
RIN_4 (AUX)
42
-6dB
TV
LIN_1 (DIG)
22
-6/-3/0/+3dB
LIN_2 (VCR)
19
-6dB
6dB
25 LTV
-3-
Bias Mute
LIN_3 (TV/OVERLAY)
16
-6dB
LIN_4 (AUX)
29
-6dB
6dB
30 PHONO_L
6dB
28 ROUT1
VCR
6dB
27 LOUT1 Mono and R/L Switch Output Disable
CXA2161R
CXA2161R
Pin Configuration
PHONO_R INTRUPT PHONO_L 30 GND_VID
VOUT_5
VOUT_6
VOUT_7
LOGIC
TRAP
MONO
RIN_4
42 VOUT_4 43 +5V_VOUT 44 VOUT_3 45 VOUT_2 46 VOUT_1 47 +5V_VID 48 VID_BIAS 49 VIN_1 50 VIN_3 51 VIN_5 52 VIN_6 53 VIN_8 54 VIN_9 55 VIN_12 56 1 VIN_13
41
40
39
38
37
36
35
34
33
32
31
29 28 ROUT1 27 LOUT1 26 RTV 25 LTV 24 +5V/12V_VCCA 23 RIN_1 22 LIN_1 21 -5V_GNDA 20 RIN_2 19 LIN_2 18 AUD_BIAS 17 RIN_3 16 LIN_3 15 +12V_DIG
2 SYNC_ID
3 VIN_11
4 VIN_10
5 VIN_7
6 VlN_4
7 VIN_2
8 GND_DIG
9 TV_FBLK
10 FBLK_IN1
11 FNC_TV
12 FBLK_IN2
13 FNC VCR
14 +5V_DIG
-4-
LlN_4
SDA
SCL
CXA2161R
Pin Description Pin No. Symbol Pin voltage [V] Equivalent circuit
VCC
Description
50 7 6
VIN_1 VIN_2 VIN_4
2.4
6 7 50
150
RGB signal inputs
VCC
2.4 51 VIN_3 2.35
150 51
RGB signal input or CVBS/Luminance signal input
VCC
2.4 52 5 VIN_5 VIN_7 3.0
20k 150 5 52
RGB signal inputs or Chrominance signal inputs
VCC 20k
53 1
VIN_6 VIN_13
3.0
150 1 53
Chrominance signal inputs
VCC
54 55 4 3 56
VIN_8 VIN_9 VIN_10 VIN_11 VIN_12
2.35
54 55 56
150 3 4
CVBS/Luminance signal inputs
VCC
47 46 45 43 39
VOUT_1 VOUT_2 VOUT_3 VOUT_4 VOUT_6
43
--
12k
45 47
39 46
RGB/CVBS signal outputs (See description of operation for pin voltages)
-5-
CXA2161R
Pin No.
Symbol
Pin voltage [V]
Equivalent circuit
VCC
Description
41
VOUT_5
1.8
12k
41
Chrominance signal output
VCC
38
VOUT_7
0.4
0.75mA 12k
38
Typically RF modulator signal output Minimum load resistance = 20k
VCC
VCC 40.8k
49
VID_BIAS
0.9
150 49 18.3k
Internal reference bias for video circuits. A capacitor is connected from this pin to GND. Typically 100nF
VCC 2k
37
TRAP
2.3
200 37
Connects trap circuit for subcarrier
VCC
2
SYNC_ID
2.5
150 2
Sync detect circuit time constant, resistor and capacitor connection pin
22 23 19 20 16 17 29 42
LIN_1 RIN_1 LIN_2 RIN_2 LIN_3 RIN_3 LIN_4 RIN_4
6.0 (Single)
22 16 23 17
VCC VCC/2 60k 60k
Audio signal inputs
0.0 (Dual)
29 19 42 20
-6-
CXA2161R
Pin No. 25 26 27 28 30 31 32
Symbol LTV RTV LOUT1 ROUT1 PHONO_L PHONO_R MONO
Pin voltage [V] 6.0 (Single)
Equivalent circuit
VCC 25 26
Description
20k
30 31 32
Audio signal outputs
0.0 (Dual)
VCC VCC
27 28
6.0 (Single) 18 AUD_BIAS 0.0 (Dual)
18
40k 150 40k
Capacitor connected to GND. Internal reference (Typically 22F) bias for audio circuits. Connected directly to GND.
VCC
10 12
FBLK_IN1 FBLK_IN2
--
150 10 12
Fast blanking signal inputs
VCC
9
TV_FBLK
--
9
Fast blanking signal output
13
FNC_VCR
--
13 120k
SCART function pin 8 input/output to VCR
VCC
11
FNC_TV
--
11
SCART function pin 8 output to TV
-7-
CXA2161R
Pin No.
Symbol
Pin voltage [V]
Equivalent circuit
VCC
Description
33 36
LOGIC INTRUPT
--
33 36
Open collector logic outputs Typically connect to +5V through 10k resistor.
35
SCL
--
34 35
8k
I2C bus clock line
34
SDA
--
I2C bus data line Digital supply
14 44 48 15 21 24 8 40
+5V_DIG +5V_VOUT +5V_VID +12V_DIG -5V_GNDA +5V/+12V_VCCA GND_DIG GND_VID 12.0 -5.0 (Dual) 0.0 (Single) 5.0 (Dual) 12.0 (Single) 0.0 0.0 5.0
Video output supply Video supply Digital supply Audio supply or Audio ground Audio supply Digital ground Video ground
-8-
CXA2161R
Electrical Characteristics Nominal conditions (Ta = 25C) Item Current consumption (Single ended supply) Current consumption (Dual supply) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 Video System Nominal conditions single supply (Ta = 25C, +5V/12V_VCCA = +12V, -5V_GNDA = 0V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Item Sync tip clamp voltage at input Chrominance bias input voltage RGB dc restore input voltage Sync tip clamp voltage at output Chrominance bias output voltage RGB dc restore output voltage Gain (Vout1 to 6) Symbol Vclmp1 Cbias1 Cbias2 RGB1 Vclmp2 Cbias3 RGB2 GVv GVRGB1 Gain (Vout1, 2, 3) GVRGB2 GVRGB3 Gain (Vout7) Mixer off Gain (Vout7) Mixer on Bandwidth (Vout1 to 6) Bandwidth (Vout7) Mixer on - No trap components Input dynamic range Output dynamic range GVYC GVYC fV3dB Conditions Vin3, Vin8, Vin9, Vin10, Vin11, Vin12 inputs. (Vin3 set to CVBS mode) (Fig. 1) Vin5, Vin7 inputs. Clamps set to Chrominance bias mode. (Fig. 1) Vin6, Vin13 inputs. (Fig. 1) Vin1, Vin2, Vin3, Vin4, Vin5, Vin7 inputs. (Vin3 & Vin5 set to RGB mode) (Fig. 1) Vout4, Vout6 outputs (Fig. 1) Vout3, Vout5 outputs (Fig. 1) Vout1, Vout2, Vout3 outputs (Fig. 1) f = 200kHz, 0.3Vp-p input , RGB Gain = 0dB (Fig. 2) f = 200kHz, 0.3Vp-p input , RGB Gain = +1dB (Fig. 2) f = 200kHz, 0.3Vp-p input , RGB Gain = +2dB (Fig. 2) f = 200kHz, 0.3Vp-p input , RGB Gain = +3dB (Fig. 2) f = 200kHz, 0.3Vp-p input (Fig. 2) f = 200kHz, 0.3Vp-p input (Fig. 2) 0.3Vp-p input, frequency where output level is -3dB with 200kHz serving as 0dB (Fig. 2) 0.3Vp-p input, frequency where output level is -3dB with 200kHz serving as 0dB (Fig. 2) 200kHz input applied to any video (Fig. 2) 200kHz input applied to any video (Fig. 2) -9- Min. -- -- -- -- -- -- -- 5.5 6.5 7.5 8.5 5.5 5.5 15 Typ. 2.4 3 2.35 2.4 0.3 1.8 0.6 6.0 7.0 8.0 9.0 6.0 5.75 22 Max. -- -- -- -- -- -- -- 6.5 7.5 8.5 9.5 6.5 6.5 -- Unit V V V V V V V dB dB dB dB dB dB MHz Conditions +12 supply, no signal, no load +5 supply, no signal, no load +12 supply, no signal, no load +5 supply, no signal, no load -5 supply, no signal, no load Min. -- -- -- -- -- Typ. 22 50 2 70 20 Max. 45 80 6 115 45 Unit mA mA mA mA mA
fV3dB VDRVI VDRVO
8 1.4 2.8
18 -- --
-- -- --
MHz Vp-p Vp-p
CXA2161R
Item Cross talk S/N ratio
Symbol Vctv S/NV
Conditions f = 4.43MHz, 1Vp-p input (Fig. 2) Ratio of 0.7Vp-p white video signal to black line noise. Weighted using CCIR 567. HPF@5kHz, LPF@5MHz. (Fig. 2)
Input pin V plus
Min. -- --
Typ. -- 74
Max. -50 --
Unit dB dB
V1
V2
Non-linearity
Lin
V1 = Pin voltage + 0.5V, V2 = Pin voltage + 1V V2 At output, non-linearity = -1 x 100 V1 x 2 (Fig. 2)
-3
0
3
%
Differential gain Differential phase
DG DP
1.7Vp-p 5-step modulated staircase. (Chrominance & Burst are 150mVp-p, 4.43MHz) (Fig. 2) As above.
-3 -3
0 0
3 3
% deg
Audio System Unless otherwise stated: input coupling capacitor 1F; output coupling capacitor 10F; load 10k. Nominal conditions single supply (Ta = 25C, +5V/12V_VCCA = +12V, -5V_GNDA = 0V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Nominal conditions dual supply (Ta = 25C, +5V/12V_VCCA = +5V, -5V_GNDA = -5V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Item Input/output pin voltage (Single supply) Input/output pin voltage (Dual supply) Output pin voltage when disabled (Dual supply) Gain Input Rin1 or Lin1 Rin1 or Lin1 Rin1 or Lin1 Rin1 or Lin1 Rin1 or Lin1 Output TV or Phono TV or Phono TV or Phono TV or Phono VCR GVA1 GVA2 GVA3 GVA4 GVA5 f = 1kHz, 0.5Vrms input. TV volume set to -0.5 0dB, RIN_1/LIN_1 amplifier = -6dB (Fig. 4) f = 1kHz, 0.5Vrms input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = -3dB (Fig. 4) f = 1kHz, 0.5Vrms input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = 0dB (Fig. 4) f = 1kHz, 0.5Vrms input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = +3dB (Fig. 4) 2.5 5.5 8.5 0 3 6 9 0 0.5 3.5 6.5 9.5 0.5 dB dB dB dB dB Symbol VAPIN1 VAPIN2 VAPIN3 Conditions No signal, no load (Fig. 3) No signal, no load (Fig. 3) No signal, no load (Fig. 3) Min. -- -- -- Typ. 6 0 0 Max. -- -- -- Unit V V V
f = 1kHz, 1Vrms input. TV volume set to -0.5 0dB, RIN_1/LIN_1 amplifier = -6dB (Fig .4) - 10 -
CXA2161R
Item Rin1 + Lin1
Symbol
Conditions
Min.
Typ. 0
Max. 0.5
Unit dB
TV GVA6 (mono mix)
f = 1kHz, 0.5Vrms stereo input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = -6dB. -0.5 TV mono switch on. (Fig. 4) f = 1kHz, 1Vrms stereo input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = -6dB. -0.5 (Note 1) (Fig. 4) f = 1kHz, 1Vrms input, TV volume set to 0dB (Fig. 4) -0.5
Rin1 + Lin1 Rin2, 3, 4 or Lin2, 3, 4 Rin1 + Lin1 Rin2 + Lin2 Rin3 + Lin3 Rin4 + Lin4 Rin2, 3, 4 Lin2, 3, 4 Rin2 + Lin2 Rin3 + Lin3 Rin4 + Lin4 Rin3
MONO TV or Phono
GVA7
0
0.5
dB
GVA9
0
0.5
dB
VCR GVA8 (mono mix)
f = 1kHz, 1Vrms stereo input. RIN_1/LIN_1 amplifier = -6dB. VCR mono switch on. -0.5 (Fig 4) f = 1kHz, 1Vrms stereo input. TV volume set to 0dB (Note 2) (Fig 4) f = 1kHz, 1Vrms input (Fig 4) f = 1kHz, 1Vrms stereo input. VCR mono switch on. (Fig 4) f = 1kHz, 1Vrms input, Lin3 has no signal Audio overlay enabled with -11dB attenuation at input RIN_3 (Fig 4) f = 1kHz, 1Vrms input Audio overlay enabled. (Fig 4) 0.3Vp-p input. Output/input gain at 30kHz with 1kHz serving as 0dB (Fig 4) 0.3Vp-p input; frequency where output level is -3dB with 1kHz serving as 0dB. No load attached (Fig 4) f = 1kHz, 0.5Vrms, unweighted response; LPF@400Hz, HPF@80kHz (Fig 4) f = 1kHz, RIN_1/LIN_1 input amplifier set to -6dB. Dual supply mode used. (Fig 4) f = 1kHz, 1Vrms input on one input, measure on any other audio output (Fig 4) Offset voltage between input and output (excluding any external series resistor) (excluding any external series resistor) f = 1kHz, 1Vrms input to two channels. Phase difference of stereo output measured f = 1kHz, 1Vrms input (at 0dB volume). HPF@20Hz, LPF@20kHz. (Fig 4) -0.5
0
0.5
dB
MONO
GVA10
0
0.5
dB
VCR
GVA11
-0.5
0
0.5
dB
VCR GVA12 (mono mix) RTV, ROUT1, Phono_R LTV, LOUT1, Phono_L
-0.5
0
0.5
dB
GVA13
-5.5
-5
-4.5
dB
Lin3
GVA14
-0.5
0
0.5
dB
Audio frequency response FAF
-0.3
0
0.3
dB
Frequency bandwidth
FBWA1
--
1
--
MHz
Distortion Input dynamic range Rin1, 2, 3, 4/Lin1, 2, 3, 4 Cross talk (Channel separation) DC offset Input impedance Rin1, 2, 3, 4/Lin1, 2, 3, 4 Output impedance Phase difference S/N ratio
THD VdA1 VctA Voff Zin1 Zout Vpda S/NA
-- 2.5 -- -30 -- -- -- 80
0.005 2.9 -- 0 120 10 0.05 93
0.2 -- -76 30 -- -- -- --
% Vrms dB mV k deg dB
Note 1) Mono switch set to mix of Rin1 & Lin1 inputs. Note 2) Mono switch set to mix of RTV & LTV after volume control. - 11 -
CXA2161R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Electronic Volume Control Volume attenuation step Mute TV I/P MUTE or VCR I/P MUTE Audio limiter level AEVC Amute f = 1kHz, 0.5Vrms input. Set by I2C (Fig 4) f = 1kHz, 1Vrms input (Fig 4) f = 1kHz, 2.5Vrms input. Measure TVp-p output with limiter switched on. (Fig 4) 1.6 -- 2 -90 2.4 -76 dB dB
Alimit
--
6.5
--
Vp-p
Digital Characteristics I2C Interface The I2C interface is compliant with Philips I2C Fast Mode specification (date April 1995). The interface is also capable of interfacing to +3.3V or +5V logic levels. Item High level input voltage Low level input voltage Low level output voltage Hysteresis of schmitt trigger input Spike suppression Fall time for SDA line SCL clock frequency Bus free time between a stop and start Symbol VIH VIL VOL VHYST tSP tF tSCL tBUF 400pF bus load I2C Bus line requirement I2C Bus line requirement I2C Bus line requirement I2C Bus line requirement With SDA, 3mA current supplied With SDA, 6mA current supplied VIH - VIL Condition Min. 2.3 0 0 0 -- -- -- 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 Typ. -- -- -- -- 0.5 -- -- -- -- -- -- -- -- -- -- -- Max. 5.5 1.5 0.4 0.6 -- 50 300 400 -- -- -- -- -- 0.9 -- -- Unit V V V V ns ns kHz s s s s s s ns s
Hold time (repeated start condition) tHD;STA Low period of SCL clock High period of SCL clock Setup time for a repeated start condition Data hold time Data setup time Setup time for stop condition tLOW tHIGH tSU;SDA tHD;DAT tSU;DAT tSU;STO
I2C Bus line requirement I2C Bus line requirement I2C Bus line requirement I2C Bus line requirement
I2C Bus line requirement
tBUF
tR
tF
tHD;STA
tHD;STA P S tLOW tSU;DAT tHIGH tSU;DAT
tSU;STA
tSU;STO Sr P
- 12 -
CXA2161R
Logic/Interrupt Output These outputs are open collector type and normally connected to +5V through a 10k resistor. Item Output low voltage Symbol DIGVOUTL IOL = 1mA Conditions Min. -- Typ. 0.15 Max. 0.4 Unit V
- 13 -
CXA2161R
Output Measurement Point
V
I2C SCL SDA
42 41 40 39 38 37 36 35 34 33 32 31 30 29 43 +5V 44 45 46 47 +5V 100nF 75 75 75 75 75 75 75 100nF 100nF 100nF 100nF 100nF 100nF 100nF 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +12V 1F +12V
Input Measurement V Point 100nF
+5V +5V 100nF 100nF 100nF 100nF 75 100nF 68k 100nF 75
75
75
75
Fig. 1. Video System (DC Test) DC measured from Pins 1, 3, 4, 5, 6, 7, 38, 39, 41, 43, 45, 46, 47, 50, 51, 52, 53, 54, 55, 56 Notes) 1. All supplies de-coupled close to supply pins 14, 15, 24, 44, 48 with 10nF and 10F capacitors. 2. All video outputs are unloaded during tests.
- 14 -
75
CXA2161R
Measurement Point
V
22k 150 150 I2C SCL SDA
42 41 40 39 38 37 36 35 34 33 32 31 30 29 150 +5V 150 150 150 +5V 100nF 75 75 75 75 75 75 75 100nF 100nF 100nF 100nF 100nF 100nF 100nF +5V 68k 100nF Input Signal 100nF 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 100nF 4 100nF 5 100nF 6 100nF 7 100nF 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +12V 1F +12V
+5V
75
75
75
75
75
Fig. 2. Video System (Gain, Dynamic Range, Bandwidth, Differential Gain, Differential Phase, Crosstalk, Linearity, Sync Detection) Signal applied to Pins 1, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 55, 56 Output signal measured from Pins 38, 39, 41, 43, 45, 46, 47 Notes) 1. All supplies de-coupled close to supply pins 14, 15, 24, 44, 48 with 10nF and 10F capacitors. 2. For tests requiring video measuring equipment with 75 input impedance, an external video line driver or buffer is used. 3. For video crosstalk tests all video inputs are terminated with 37.5
- 15 -
75
CXA2161R
Output Measurement Point
V
I2C SCL SDA
42 41 40 39 38 37 36 35 34 33 32 31 30 29 43 +5V 44 45 46 47 +5V 100nF 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 +12V 24 23 22 21 20 19 18 17 16 15 +12V 1F -5V +5V
+5V Input Measurement V Point
Fig. 3. Audio System (DC Tests)
DC measured from Pins 16, 17, 19, 20, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 42 Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration. 2. All supplies de-coupled close to supply pins 14, 15, 21, 24, 44, 48 with 10nF and 10F capacitors.
- 16 -
CXA2161R
10k Measurement Point
V
1k
10F
10F
10F
1F
I2C SCL SDA
42 41 40 39 38 37 36 35 34 33 32 31 30 29 43 +5V 44 45 46 47 +5V 100nF 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Input Signal 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1F 1F +12V 1k 1k 1F 1F 1F 1F 1F 10F 10F 10F 10F +12V +5V 1k 1k
1F
1k
-5V
1k 1k
+5V
Fig. 4. Audio System (Single Supply -- Gain, Bandwidth, Signal to Noise, Electronic Volume, Zero Cross Detection, Limiter) (Dual Supply -- Distortion, Dynamic Range, Crosstalk)
Signal applied to Pins 16, 17, 19, 20, 22, 23, 29, 42 Output signal measured from Pins 25, 26, 27, 28, 30, 31, 32 Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration. 2. All supplies de-coupled close to supply pins 14, 15, 21, 24, 44, 48 with 10nF and 10F capacitors.
- 17 -
CXA2161R
I2C Control Data Format S Slave address A S: Start condition Address = 90H I2C Data Structure (write mode) b7 Address Data1 Data2 Data3 Data4 Data5 Data6 Data7 1 b6 0 b5 0 b4 1 b3 0 VOLUME CONTROL TV MONO SWITCH VCR MONO SWITCH FNC LEVEL FNC FOLLOW RGB GAIN VIN5 CLAMP ENABLE VOUT5 VIN7 CLAMP ENABLE VOUT4 TV AUDIO SELECT VCR AUDIO SELECT FNC DIR b2 0 b1 0 b0 0 = Write TV AUD MUTE PHONO BYPASS OVERLAY ENABLE DATA1 A DATA2 A DATA3 A DATA4 A DATAn A P
A: Acknowledge
P: Stop condition
RIN1/LIN1 GAIN CONTROL MONO SWITCH TV AUD MUTE TV INPUT MUTE TV VOL BYPASS OUTPUT LIMIT LOGIC LEVEL
FAST BLANK
VCR VIDEO SWITCH VCR INPUT MUTE ZCD SYNC SEL VOUT5 0V ENABLE VOUT6
TV VIDEO SWITCH VIN3 CLAMP ENABLE VOUT3 MIXER CONTROL ENABLE VOUT2 ENABLE VOUT1
I2C Data Structure (read mode) b7 Address Data 1 NOT USED b6 0 NOT USED b5 0 ZERO CROSS STATUS b4 1 P.O.D. b3 0 NOT USED b2 0 SYNC DETECT b1 0 b0 1 = Read FNC_VCR
Note) ZCD = Zero Cross Detect P.O.D. = Power on Detect
- 18 -
CXA2161R
Video I2C Write Structure Video Switch 1: TV Output [Data 5 Bits 0, 1, 2] Switch setting Blue Vout1 Green Vout2 Encoder Green VIN3 Bias R/C Vout3 Encoder Red VIN5 Encoder Chrominance VIN6 CVBS/Y Vout4 Encoder CVBS VIN8 Encoder Luminance VIN9 Comment Digital encoder RGB or CVBS
Encoder 0 xxxxx000 Blue VIN1 1 xxxxx001 Bias
Digital encoder Y/C
2 xxxxx010
VCR Blue VIN2
VCR VCR Green Chrominance/Red VIN4 VIN7 Bias Bias Encoder Chrominance VIN5 Encoder Red VIN5 Aux Chrominance VIN13 Bias
VCR CVBS/Y VCR Y/C or RGB VIN10 TV CVBS VIN11 Encoder Luminance VIN3 Aux CVBS VIN12 Aux CVBS/Y VIN12 Bias TV
3 xxxxx011 Bias
4 xxxxx100 Bias Encoder 5 xxxxx101 Blue VIN1 6 xxxxx110 Bias 7 xxxxx111 Bias
Bias Encoder Green VIN3 Bias Bias
Digital encoder Y/C
Encoder RGB and Aux CVBS
Aux Y/C or CVBS Video mute (Power on default)
After power on all TV outputs are off (high impedance output) and muted. TV RGB GAIN Control [Data 5 Bits 3, 4] I2C setting RGB GAIN 0 xxx00xxx 1 xxx01xxx 2 xxx10xxx 3 xxx11xxx Extra gain/dB 0 (Power on default) +1 +2 +3
- 19 -
CXA2161R
Video Switch 2: VCR Output [Data 5 Bits 5, 6, 7] Switch setting 0 1 2 3 4 5 6 7 000xxxxx 001xxxxx 010xxxxx 011xxxxx 100xxxxx 101xxxxx 110xxxxx 111xxxxx Chrominance Vout5 CVBS/Y Vout6 Comment Digital encoder Y/C Digital encoder Y/C or CVBS VCR Y/C TV CVBS Encoder Y/C Aux CVBS Aux Y/C or CVBS Video mute (Power on default)
Encoder Chrominance Encoder CVBS/Y VIN5 VIN8 Encoder Chrominance Encoder CVBS/Y VIN6 VIN9 VCR Chrominance VIN7 Bias VCR CVBS/Y VIN10 TV CVBS VIN11
Encoder Chrominance Encoder Luminance VIN5 VIN3 Bias Aux Chrominance VIN13 Bias Aux CVBS VIN12 Aux CVBS/Y VIN12 Bias
After power on VCR outputs are off (high impedance) and muted. MIXER CONTROL [Data 6 Bits 0, 1] I2C setting 0 1 2 3 xxxxxx00 xxxxxx01 xxxxxx10 xxxxxx11 Mixer Output Vout7 No mix, Vout7 = Vout4 (CVBS) Mix of Vout4 (Y) + Vout3 (C) No mix, Vout7 = Vin8 (CVBS) No mix, Vout7 = Vout4 (CVBS) (Power on default)
Input Clamp Control VIN3 Clamp [Data 6 Bit 2] xxxxx0xx = GREEN input on VIN3. DC restore clamp active. (Power on default.) xxxxx1xx = CVBS input on VIN3. Sync tip clamp active. Input Clamp Control VIN7 Clamp [Data 6 Bit 3] xxxx0xxx = CHROMINANCE input on VIN7. Chrominance bias applied. (Power on default.) xxxx1xxx = RED input on VIN7. DC restore clamp applied. Input Clamp Control VIN5 Clamp [Data 6 Bit 4] xxx0xxxx = RED input on VIN5. DC restore clamp applied. (Power on default.) xxx1xxxx = CHROMINANCE input on VIN5. Chrominance bias applied.
- 20 -
CXA2161R
Sync Select Control for RGB DC Restore Circuits SYNC_SEL [Data 6 Bits 5, 6] When the TV output is set to RGB + Y/CVBS mode. Then it is necessary to select the input that contains the sync information for the RGB signal. This will normally be the digital encoder CVBS or VCR CVBS input. I2C setting SYNC SEL 0 1 2 3 x00xxxxx x01xxxxx x10xxxxx x11xxxxx Input with sync VIN8 (Power on default) VIN9 VIN10 VIN12
Standby Mode Control [Data 7 Bits 0, 1, 2, 3, 4, 5] The video outputs VOUT1, 2, 3, 4, 5, 6 can be individually turned off using data byte 7. 0 = Video output off. (Power on default) 1 = Video output on. Note) When switched off, the video outputs are in a high impedance state. With a normal 150 load, the outputs will be pulled to 0V. Bi-directional Line Control on VCR Scart. Vout5_0V [Data 7 Bit 6] x0xxxxxx = Vout5 active. Connected to input specified in VCR switch table. x1xxxxxx = Vout5 set to 0V (Power on default)
I = 6mA (When set to 0V mode) 75 6dB Vout5 0V Vout5 Chrominance out
VCR Scart Pin 15 Red in Chrominance In Chrominance Out
VIN_7 Red in Chrominance in
Fig 5. Bi-directional Line to VCR As Pin 15 on the VCR scart can be bi-directional, either chrominance output or red/chrominance input, it is necessary for output Vout5 to be individually controlled. When the VCR inputs red/chrominance signals, the output Vout5 is set to 0V giving the required line impedance of 75.
- 21 -
CXA2161R
I2C Audio Signal Control Channel Select TV (Phono), VCR [Data 2, 3 Bits 1, 2] Switch setting 0 1 2 3 xxxxx00x xxxxx01x xxxxx10x xxxxx11x RTV, Phono_R, ROUT1 Rin1 Rin2 Rin3 Rin4 LTV, Phono_L, LOUT1 Lin1 Lin2 Lin3 Lin4
After power on Rin4/Lin4 are selected. Mono Switch TV [Data 2 Bits 3, 4, 5] Switch setting 0 1 2 3 4 5 6 7 xx000xxx xx001xxx xx010xxx xx011xxx xx100xxx xx101xxx xx110xxx xx111xxx Connection to R channel output R (R + L mix) L R L R R R Connection to L channel output L (R + L mix) R R L L L L Normal Mono mix Channel swap Right channel only Left channel only Normal Normal Normal (power on default) Comment
Mono Switch VCR [Data 3 Bits 3, 4, 5] Switch setting 0 1 2 3 4 5 6 xx000xxx xx001xxx xx010xxx xx011xxx xx100xxx xx101xxx xx110xxx Connection to R channel output R (R + L mix) L R L R R Connection to L channel output L (R + L mix) R R L L L Normal Mono mix Channel swap Right channel only Left channel only Normal Normal All audio outputs disabled (RTV, LTV, PHONO_R, PHONO_L, MONO, ROUT1, LOUT1) (power on default) Comment
7
xx111xxx
X
X
- 22 -
CXA2161R
PHONO BYPASS [Data 2 Bit 0] xxxxxxx0 = Phono outputs connected after volume control block. (Power on default) xxxxxxx1 = Phono outputs connected before volume control block. TV VOL BYPASS [Data 2 Bit 6] x0xxxxxx = TV outputs connected after volume control block. (Power on default) x1xxxxxx = TV outputs connected before volume control block. MONO SWITCH [Data 2 Bit 7] 0xxxxxxx = Mono output connected to mix of TV R + L channels. (Power on default) 1xxxxxxx = Mono output connected to mix of RIN1 + LIN1 inputs. VOLUME CONTROL [Data 1 Bits 1, 2, 3, 4, 5] Setting 0 1 2 3 4 5 6 7 8 9 10 11 xx00000x xx00001x xx00010x xx00011x xx00100x xx00101x xx00110x xx00111x xx01000x xx01001x xx01010x xx01011x : 31 xx11111x Volume gain +6dB +4dB +2dB 0dB (power on default) -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB : -56dB
AUDIO RIN1/LIN1 GAIN [Data 1 Bits 6, 7] Setting 0 1 2 3 00xxxxxx 01xxxxxx 10xxxxxx 11xxxxxx Input attenuation -6dB (Power on default) (Note 1) -3dB +0dB +3dB
Note 1) The power on default is -6dB. As the output amplifiers have a nominal +6dB gain the overall input to output gain is 0dB.
- 23 -
CXA2161R
OVERLAY ENABLE [Data3 Bit 0] xxxxxxx0 = Overlay off (Power on default) xxxxxxx1 = Overlay on: Rin3 and Lin3 are mixed and added to Rin1, Lin1 channels. Rin1 and Lin1 are attenuated by 16dB before mixing with the tone.
TV Mute and Zero Cross Operation When the zero cross is switched on (ZCD = 1), volume control changes are only implemented when the audio signal passes though the zero cross point. Similarly, when a mute instruction is sent, the TV outputs are only muted when the signal passes the zero cross point. This eliminates any click noise. There are two TV audio mute control bits in the bus map. By having two bits it allows the TV outputs to be muted, the TV channel changed and then un-muted all in one I2C write operation. The normal structure for a click free audio channel change is as follows: Data 1: Mute the TV audio output with the ZCD switched on. Data 2: Change the TV audio source. Data 3: Un-mute the TV audio output again with the ZCD switched on. Operation of the Mute circuit TV Aud Mute [Data 1 Bit 0] [Data 3 Bit 7] 0 0 1 1 ZCD [Data 7 Bit 7] 0 1 0 1 TV, Phono and Mono output Un-mute immediately Un-mute on next zero cross Mute immediately Mute on next zero cross
After power on TV Audio Mute = 1 and ZCD are set to 1. TV INPUT MUTE [Data 4 Bit 7] 0xxxxxxx = The input to the TV switch is not muted. 1xxxxxxx = The input to the TV switch is muted. (power on default) VCR INPUT MUTE [Data 6 Bit 7] 0xxxxxxx = The input to the VCR switch is not muted. 1xxxxxxx = The input to the VCR switch is muted. (power on default) OUTPUT LIMIT [Data 3 Bit 6] This will limit the output level of the volume control block to 2.2Vrms maximum. 0xxxxxxx = The volume control outputs are not limited. (power on default) 1xxxxxxx = The volume control outputs are limited to 2.2Vrms.
- 24 -
CXA2161R
Fast Blanking Operation (Pin 16 on SCART), FBLK The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and is defined as follows, Fast blanking output at scart, 1. CVBS mode: Scart pin voltage = 0 to 0.4V 2. RGB mode: Scart pin voltage = 1 to 3.0V The threshold voltage is approximately 0.75V at the scart input. Fast Blanking I2C Control In the CXA2161R, there are two fast blanking inputs, one associated with the digital encoder input (FBLK_IN1) and another associated with the VCR RGB/CVBS input (FBLK_IN2). These can be selected and switched to the output using an I2C instruction. In addition, the fast blank output pin can be set to a constant 0V or +3.5V by means of the I2C control. Hence there are four possible states. These are set according to the following table. FAST_BLANK [Data 4 Bits 0, 1] I2C setting BLANK_LEVEL 0 1 2 3 xxxxxx00 xxxxxx01 xxxxxx10 xxxxxx11 Fast blank output pin voltage 0V (Power on default) Same level as Fast Blank in 1 (0/+3.5V) Same level as Fast Blank in 2 (0/+3.5V) +3.5V
Fast Blank Output Interface The Fast Blanking output pin is connected to the scart via a 75 resistor.
TV_FBLK 0V/+3.5V
75
TV 75 Scart line 16
CXA2161R
Fig. 6. Fast Blanking Output Interface
- 25 -
CXA2161R
Function Switching Operation (Pin 8 on scart) The function switch facility is designed to read the status of the SCART function Pin 8 from the VCR scart connector and store this in the status register. Both, VCR and TV function lines can be set to outputs and controlled by I2C. The TV function line has two modes, the first being control via I2C and secondly the follow mode where the output will follow the same state as the VCR input. Setting the Direction for the Function Lines The input and control for the function lines is set by the FNC_DIR and FNC_FOLLOW bits. FNC_FOLLOW [Data 4 Bit 3] 0 0 1 1 FNC_DIR [Data 4 Bit 2] 0 1 0 1 VCR Pin 8 Input (Level stored in read register) Output Controlled by FNC_LEVEL Input (Level stored in read register) TV Pin 8 Output Controlled by FNC_LEVEL Output Holds previous level Output Follows same level as VCR input
Output (Both set to same voltage controlled by FNC_LEVEL)
FNC_LEVEL [Data 4 Bits 4, 5] These bits set the voltage at the (TV_FNC or VCR_FNC) outputs. The output is determined by the table above. I2C control FNC_LEVEL 0 1 2 3 xx00xxxx xx01xxxx xx10xxxx xx11xxxx < 2V > 4.5V, < 7V < 2V > 9.5V Voltage at output Internal TV External scart input 16:9 mode Internal TV External scart input 4:3 mode Mode
Note) After power on the output is internal TV mode ie. 0V at the pin.
+12V_DIG > 4.5 < 7V < 2V FNC_VCR 10k FNC_TV
> 9.5V
Inside TV
Scart Pin 8
Scart Pin 8
10k
Fig. 7. TV Function Switch Output
- 26 -
CXA2161R
Logic and Interrupt Output These open collector output pins can be used for an interrupt line to a microprocessor or as a general purpose logic output. Interrupt Output The INTRUPT pin will become a current sink for approximately 2s when the VCR input function line changes from: a) 0 to 6V, 6 to 0V b) 0 to 12V, 12 to 0V c) 6 to 12V, 12 to 6V This pin will normally be connected to +5V through a 10k resistor. Logic Output The logic output level can be changed using the logic output bit in the I2C register, LOGIC_LEVEL. LOGIC LEVEL [Data 4 Bit 6] x0xxxxxx = Current sink mode resulting in < 0.4V saturation voltage on logic pin. (Power on default) x1xxxxxx = Open collector/high output impedance on logic pin. Imax during current sink = 1mA
+3 to 14V 10k External resistors 10k To Microprocessor 2s
INTRUPT LOGIC
Fig. 8. INTRUPT and Logic Line Interface
- 27 -
CXA2161R
Read Mode Status Register The following information can be read from the status register: FNC VCR [Bits 0, 1] The status register bits 0, 1 hold the level of the input function line Input pin voltage FNC_VCR 0 to +2V (default) +4.5 to +7V +9.5 to +12V SCART mode b1 (Internal) (16:9 External) (4:3 External) 0 0 1 Data 8 b0 0 1 1
SYNC DETECT [Bit 2] Once a valid sync signal is detected on the input selected by SYNC_SELECT this bit is set to 1. The bit is reset to 0 every time the SYNC_SELECT is changed. It is assumed that when a video input is in-active then the input level will be 0V with minimum noise. POD (Power on Detect) [Bit 4] This bit is set to 1 after power on. It is then changed to 0 after the first I2C read. It is used to detect if the supply has been corrupted. If the POR bit is read as 1 at any time then the IC should be re-initialized to the correct I2C settings. Zero Cross Status [Bit 5] This audio function is used to determine if an input audio signal has passed the zero cross point. For dual supply operation the zero cross point is 0V. For Single supply, the zero cross point is approximately 6V.
Zero cross point Input signal
Bias voltage
Fig. 9. Zero Cross Point 0 = No zero cross detected 1 = Signal has passed through zero cross point.
- 28 -
CXA2161R
Description of Operation Video Section Inputs and Outputs The video section comprises of thirteen (13) high impedance inputs switched through to seven (7) video outputs. An internal +6dB amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation that occurs at the 75 series output resistor. The outputs VOUT_1 to VOUT_6 are capable of driving 150 loads. Output VOUT_7 is designed to interface to an RF Modulator but requires an external buffer to drive a 75 load. Composite/Luminance Inputs The 4 composite (or luminance) inputs are ac coupled to the input pins. The signals are first sync tip clamped to a set level. These clamps are permanently active, therefore these inputs should only be used for signals with a sync.
VCC = +5V VCC = +5V
1Vp-p 2Vp-p 2.4V 0V Input signal 0.3V 0V Output signal
Fig. 10. CVBS/Y Waveforms RGB Inputs The RGB inputs are ac coupled to the input pins. The inputs have a dc restore circuit, which is used to set the blanking level to a fixed voltage. The clamps are controlled by the timing signal provided by the sync detect circuit. It is necessary to select the correct luma or CVBS signal associated with the RGB inputs for the sync select circuit. It is assumed that a sync signal will not be present on any of the RGB input signals. For inputs that can be either red or chrominance then the clamp can be switched between the dc restore mode (for red input) and average level bias (for chrominance). The RGB signals are fed through additional amplifiers that are controlled via I2C. These allow the nominal 0.7Vp-p signal to be increased to 0.8Vp-p, 0.9Vp-p or 1Vp-p. When the TV output is in Y/C mode, the RGB gain should be set to 0dB to prevent over amplification of the chrominance output.
VCC = +5V VCC = +5V
0.7Vp-p 2.4V 0V Input signal 0.6V 0V Output signal
1.4Vp-p
Fig. 11. RGB Waveforms - 29 -
CXA2161R
Sync Detection Circuit The clamp signals, used to restore the RGB level, are generated from the sync detect circuit. By using the SYNC_SELECT control bits, the 4 different CVBS/Y inputs may be selected. Once selected, the clamped signal is compared with a threshold voltage 65mV above the tip level. If the signal is less than this threshold it is not passed to the next block. If greater than the threshold, it is passed to the discrimination circuit that checks that the duty cycle is greater than 91%. The discrimination block also contains a time constant which, when a sync is detected, holds the status line high for at least 11 video lines. If a valid sync signal is detected the SYNC_DETECT bit in the read register is set to 1.
+5V_VID LOGIC Duty Discrimination
RGB input clamp timing
DIG CVBS/Y DIG CVBS/Y VCR CVBS/Y AUX CVBS/Y
SYNC_SELECT Status register SYNC_DETECT bit
68k External R/C SYNC_ID 0.1F GND_VID Comparator
Sync detect circuit
I 2C
Fig. 12. Sync Detection Circuit Chrominance Inputs The chrominance signals are ac coupled to the input pins. The inputs have a fixed dc bias that sets the average level to approximately 3V for VIN_5 & VIN_7 and 2.35V for VIN_6 & VIN_13. For inputs that can also be RED signals the input circuit can be switched to the dc restore mode. Typical waveforms:
VCC = +5V VCC = +5V
2.35 or 3V
0.7Vp-p
1.8V 0V Chrominance input pin voltage 0V Chrominance output pin voltage
1.4Vp-p
Fig. 13. Chrominance Waveforms
- 30 -
CXA2161R
Y/C Mixer A Y/C mixer can be used for mixing Luminance and Chrominance signals for use with an external RF modulator connected to VOUT_7. The Y/C mixer is controlled via the I2C data bus. The signal may be a mix of the TV Y/C signals or simply the TV CVBS signal. It is also possible to select the CVBS signal from the digital encoder. The circuit is shown in Fig 14. with a trap circuit used to give 6dB attenuation at 4.43MHz of the Luminance signal. The output VOUT_7 cannot drive loads higher than 20k resistive. If it is necessary to drive a 75 load with this output then an external emitter follower arrangement should be used.
R/C
0, 1, 2 or 3dB
6dB
VOUT_3
CVBS/Y
6dB Mixer switch 6dB
VOUT_4
2k VIN_8 = CVBS
VOUT_7 TRAP R
For recommended values: see application circuit
C L
Fig. 14. Internal Y/C Mixer Circuit Switching the Video Outputs Off Each video output can be individually turned off using the I2C. When turned off, the output is set to a high impedance state and hence the current consumption and power dissipation is reduced. After power on, all the video outputs are set to the high impedance state.
- 31 -
CXA2161R
Typical Video Interface Circuits Single or Dual Supply
100nF VIN_1 to VIN_13
75 Scart
Fig. 15. Video Input Interface
75 VOUT_1 to VOUT_6 75 (Line C = 400pF max) Scart
Fig. 16. Video Output Interface
- 32 -
CXA2161R
Audio Section Inputs and Outputs The audio system consists of 4 stereo inputs, 2 stereo outputs and separate mono and Phono outputs. The stereo outputs can be connected to any one of the 4 stereo inputs. All audio inputs have a -6dB attenuator except RIN_1 and LIN_1. Therefore, the net gain of the audio system from input to output is 0dB, as an amplifier having +6dB of gain follows the internal switch. The stereo input RIN_1/LIN_1 has extra switchable gain as this input is typically connected to an audio DAC with full scale of 1Vrms or less. The output impedance of each audio amplifier is near zero, and may be directly coupled to the scart in the case of a dual supply but must be ac coupled through a capacitor (typically 10F) for the single supply case. The outputs are capable of driving 600 loads. The user may add additional low pass filters to the outputs. TV Output Switching The TV audio section is composed of an audio switch followed by a volume control stage. The volume is adjustable from +6dB to -56dB in 2dB steps. The volume control block includes a switchable limiter function to prevent the output signals exceeding 2.2Vrms. When activated, the output signals from the volume control block will be clamped to 2.2Vrms. A mono switch that allows the mixed R + L signal to be switched to the R and L output channels follows the volume control section. The mono switch is also capable of routing the R signal onto both R and L channel and similarly the L signal to the R and L output channels. This may be used if the audio channels consist of two different languages. It is also capable of swapping the R and L channels. TV Mute This I2C mute function acts only on the TV, Phono and mono audio circuits. Audio mute will be implemented after an audio zero cross detection to reduce click noise if ZCD = 1. Zero Cross Detector (ZCD) The zero cross detector reduces the effect of click noise when implementing a volume change or an audio mute. The volume change or mute instruction sent by I2C will only be implemented when a minimal (ie zero cross) signal amplitude is detected. It can be seen from the I2C write format that the same mute bit occurs in DATA1 and DATA3. This allows the software to action a mute, then after a delay (1/Audio_freq (min)) make any suitable changes to the audio source and then un-mute the output buffer. Such a period provides ample time to allow any audio signals to pass the zero cross point before the signal source is changed. VCR Output Switching The outputs ROUT1, LOUT1 have a fixed gain of 0dB from the input. If any attenuation is required then it is possible to insert a series resistance on the input. Again, this output has a mono switching block that allows the mixed R + L to be inserted on both output channels.
- 33 -
CXA2161R
Phono outputs There is a stereo Phono output that carries the same signal as the TV output. This is typically used for connection to a hi-fi. The signal level of the Phono outputs is normally the same as the TV outputs however it is possible to bypass the volume section and set the Phono outputs to a fixed level. If any attenuation is required then this can be done externally. Mono Output The mono output for the RF modulator has two settings. The first is a mix of the TV R + L channels. In this case, the output signal will have the same volume control as the RTV/LTV outputs. The second setting is a mix of the audio DAC inputs (RIN_1 + LIN_1). In this setting the output will always have fixed volume and if the tone overlay is used, this will appear on the output. Audio Overlay The inputs RIN_3, LIN_3 may be used for a normal stereo audio input or alternatively to overlay an external audio source onto the TV outputs. This may be a tone or voice. The R and L inputs are mixed and then added equally to the RIN_1 and LIN_1 inputs. The I2C control bit Audio overlay enable is used to switch on this facility and control the attenuator block on RIN_3 which is set to give an extra 5dB of attenuation when switched on. If two tones are used then it is up to the user to switch them individually before the A/V switch. When the tone overlay is activated, the signals RIN_1, LIN_1 are attenuated by approximately 16dB before mixing. Audio Disable All the audio outputs may be disabled using the Audio Output Disable function in the VCR mono switching block [Data Byte 3 Bits 3, 4, 5 set to 111]. This disable mode is different from the normal mute as it can be used for power reduction in stand by modes.
- 34 -
CXA2161R
Typical Audio Interface Circuits Supply type 1: Dual supply
0.1F RIN_1, 2, 3, 4 LIN_1, 2, 3, 4
Scart
Fig. 17. Audio Input Interface
RTV, LTV ROUT1, LOUT1
Optional protection resistor
PHONO_R, PHONO_L
Optional protection resistor
600 to 10k (Line C = 400pF max) Scart
MONO
To RF modulator
600 to 10k (Line C = 400pF max)
Fig. 18. Audio Output Interface Supply type 2: Single supply
0.1F RIN_1, 2, 3, 4 LIN_1, 2, 3, 4
Scart
Fig. 19. Audio Input Interface
RTV, LTV ROUT1, LOUT1
10F 600 to 10k (Line C = 400pF max)
PHONO_R, PHONO_L 10F MONO To RF modulator
Scart
600 to 10k (Line C = 400pF max)
The user may use larger capacitors if required.
Fig. 20. Audio Output Interface - 35 -
CXA2161R
Application in Set Top Box
Inputs B G R CVBS C Y FAST BLANKING VIN_1 VIN_3 VIN_5 VIN_8 VIN_6 VIN_9 FBLK_IN1 Outputs
Digtal Encoder
VOUT_1 VOUT_2 VOUT_3 VOUT_4 TV_FBLK TV_FNC
B G TV R/C CVBS/Y FAST BLANKING FUNCTION SWITCH
B G VCR R/C CVBS/Y FAST BLANKING FUNCTION SWITCH
CXA2161R VIN_2 A/V switch VIN_4 VOUT_5 VIN_7 VOUT_6 VIN_10 FBLK_IN2 VCR_FNC
C CVBS/Y
VCR
VOUT_7 TV CVBS CVBS/Y AUX C VIN_11 VIN_12 VIN_13
CVBS
RF MOD.
Fig. 21. Video Application with 6 Output Digital Encoder
Inputs B G/CVBS Digtal R/C Encoder CVBS/Y FAST BLANKING VIN_1 VIN_3 VIN_5 VIN_8 FBLK_IN1
Outputs
C Analogue CVBS/Y Sat. B G VCR R/C CVBS/Y FAST BLANKING FUNCTION SWITCH
VIN_6 VIN_9
VOUT_1 VOUT_2 VOUT_3 VOUT_4 TV_FBLK TV_FNC
B G TV R/C CVBS/Y FAST BLANKING FUNCTION SWITCH
CXA2161R VIN_2 A/V switch VIN_4 VOUT_5 VIN_7 VOUT_6 VIN_10 FBLK_IN2 VCR_FNC
C CVBS/Y
VCR
VOUT_7 TV CVBS VIN_11
CVBS
RF MOD.
CVBS/Y AUX C
VIN12 VIN13
Fig. 22. Video Application with 4 Output Digital Encoder
- 36 -
CXA2161R
Audio Application
STB audio DAC full scale = 2Vrms
RIN_1 LIN_1
RTV LTV
L
TV
R
VCR fs = 2Vrms
RIN_2 LIN_2
ROUT1 LOUT1
VCR
TV or STB generated voice/ tone
RIN_3 LIN_3
PHONO_R PHONO_L
L Hi-Fi
R
AUX fs = 2Vrms
RIN_4 LIN_4
MONO
RF Modulator
TV (Mono)
Fig. 23. Audio Application
- 37 -
CXA2161R
Supply Connections
+5V (0.25V)
+12V (0.6V)
+5V/12V_VCCA AUD_BIAS
+12V_DIG
+5V_DIG
+5V_VID
+5V_VOUT VID_BIAS
-5V_GNDA
GND_DIG
GND_VID
0.1F
-5V (0.25V)
Fig. 24. Dual Supply
+12V (0.6V)
+5V (0.25V)
+5V/12V_VCCA AUD_BIAS
+12V_DIG
+5V_DIG
+5V_VID
+5V_VOUT VID_BIAS
22F
-5V_GNDA
GND_DIG
GND_VID
0.1F
Fig. 25. Single Ended Supply
- 38 -
Application Circuit 1 Single Ended Supply
VOUT_7 to RF Modulator Supplies +5V GND AUX_L +12V 10F SCL SDA +5V 100nF 10F 100nF 100nF 12pF AUX_R GND
TV
TV_CVBS_IN GND 10F 10F 10F 100nF 1.8k 10k 10k 34 SDA LlN_4 28 10F 33 32 31 30 29 42 RIN_4 SCL TRAP TV_CVBS_OUT 75 ROUT1 LOUT1 27 10F TV_RED/C 45 VOUT_3 75 TV_GREEN 46 VOUT_2 75 TV_BLUE 47 VOUT_1 75 +5V 49 VID_BIAS DIG_BLUE 50 VIN_1 75 51 VIN_3 100nF 52 VIN_5 100nF 53 VIN_6 100nF 54 VIN_8 100nF 100nF 100nF 1 100nF DIG_FBLANK 75 +5V 75 100nF 75 75 75 68k RIN_3 17 100nF TV_LIN VIN_10 VIN_7 VlN_4 VIN_2 GND_DIG TV_FBLK FBLK_IN1 FNC_TV FBLK_IN2 FNC VCR +5V_ DIG LIN_3 16 +12V_ DIG 15 VIN_11 3 4 5 6 7 8
100nF 100nF 100nF 100nF 100nF
100H
20 +5V
21
VCR_RED/C
TV_FBLANK 100nF Place close to Pin 24 41 40 39 38 37 36 35 75 75
16
GND
14
15
GND
12
13
TV_RED/C
10
11
GND
VCR_CVBS_OUT
GND
18
19
GND
17
TV_CVBS_OUT
Place close to Pin 14 Place close to Pin 44
TV_FNC LOGIC MONO
8
9
TV_GREEN
TV_LIN
6 VOUT_5 VOUT_6 VOUT_7 INTRUPT
7
GND
GND +5V
4 43 VOUT_4 44 +5V_VOUT RTV 26
5
TV_BLUE
PHONO_R
PHONO_L
1
GND_VID
TV_RIN
2
3
GND
VCR_ROUT VCR_LOUT TV_ROUT 10F
TV_LOUT
TV_ROUT
LTV 25 +5V/12V_VCCA 24 RIN_1 23 100nF CXA2161R LIN_1 22 100nF -5V_GNDA 21 RIN_2 20 100nF LIN_2 19 100nF AUD_BIAS 18 GND 10F +12V
TV_LOUT Digital Audio Input DIGITAL_AUDIO_R DIGITAL_AUDIO_L
48 +5V_VID
VCR_CVBS_IN AUX_C
20
GND
18
19
GND
AUX video inputs 75
VIN_13 SYNC_ID
10
11
75
75
GND
TV_CVBS_IN
VCR_RED/C
VCR_GREEN
VCR_BLUE
VCR_CVBS_IN
VCR_FBLANK
VCR_FNC
VCR_RIN
2
3
1
VCR_LOUT
CXA2161R
VCR_ROUT
TV_FBLANK
VCR_LIN
4
5
GND
TV_FNC
VCR_FNC
8
9
VCR_GREEN
6
7
GND
10k
VCR_BLUE
+5V
- 39 -
100nF 100nF DIG_GREEN DIG_RED DIG_CHROMA DIG_CVBS DIG_LUMA AUX_Y/CVBS 75 55 VIN_9 VIN_12 56 2 75 75 75 75 9
VCR_RIN VCR_LIN
Digital encoder inputs
22F TV_RIN
VCR
100nF +12V 10 11 12 13 14
21
VCR_FBLANK
16
17
VCR_CVBS_OUT
GND
14
15
GND
12
13
VCR_RED/C
Digital fast blank
75
GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Application Circuit 2 Dual Supply
VOUT_7 to RF Modulator Supplies AUX_R GND GND AUX_L 10F SCL SDA +5V 100nF 100nF 75 1.8k 10k 10k 34 SDA LlN_4 28 33 32 31 30 29 VCR_ROUT VCR_LOUT TV_ROUT RTV 26 LTV 25 +5V/12V_VCCA 24 RIN_1 23 100nF 49 VID_BIAS DIG_BLUE 50 VIN_1 75 51 VIN_3 100nF 52 VIN_5 100nF 53 VIN_6 100nF 54 VIN_8 100nF 100nF 100nF 1 75 100nF 68k +5V 75 100nF 75 75 75 RIN_3 17 100nF TV_LIN VIN_10 VIN_7 VlN_4 VIN_2 GND_DIG TV_FBLK FBLK_IN1 FNC_TV FBLK_IN2 FNC VCR +5V_ DIG LIN_3 16 +12V_ DIG 15 VIN_11 3 4 5 6 7 8
100nF 100nF 100nF 100nF 100nF
Place close to Pin 14 +5V 100nF +12V 100nF 10F VCC
TV 12pF +5V
100H
TV_CVBS_IN GND 100nF 75 100nF Place close to Pin 24 -5V
20
21
Place close to Pin 44
VCR_RED/C
TV_FBLANK
16
GND
14
15
GND
VCR_CVBS_OUT
GND
18
19
GND
17
TV_CVBS_OUT
12
13
TV_RED/C
10F Place close to Pin 21
10 42 TRAP TV_CVBS_OUT 75 ROUT1 LOUT1 27 +5V TV_RED/C 45 VOUT_3 75 TV_GREEN 46 VOUT_2 75 TV_BLUE 47 VOUT_1 75 +5V CXA2161R 48 +5V_VID 43 VOUT_4 44 +5V_VOUT RIN_4 SCL 41 40 39 38 37 36 35
11
GND
TV_FNC LOGIC MONO
8
9
TV_GREEN
TV_LIN
6 VOUT_5 VOUT_6 VOUT_7 INTRUPT
7
GND
GND
4
5
TV_BLUE
TV_ROUT
PHONO_R
PHONO_L
1
GND_VID
TV_RIN
2
3
GND
TV_LOUT
TV_LOUT +5V Digital Audio Input DIGITAL_AUDIO_R DIGITAL_AUDIO_L LIN_1 22 100nF -5V_GNDA 21 RIN_2 20 100nF LIN_2 19 100nF AUD_BIAS 18 TV_RIN VCR_LIN -5V VCR_RIN
VCR_CVBS_IN AUX_C DIG_FBLANK
20
GND
18
19
GND
AUX video inputs 75
VIN_13 SYNC_ID
10
11
75
75
GND
TV_CVBS_IN
VCR_RED/C
VCR_GREEN
VCR_BLUE
VCR_CVBS_IN
VCR_FBLANK
VCR_FNC
CXA2161R
VCR_RIN
2
3
1
VCR_LOUT
VCR_ROUT
TV_FBLANK
VCR_LIN
4
5
GND
TV_FNC
VCR_FNC
8
9
VCR_GREEN
6
7
GND
10k
VCR_BLUE
+5V
- 40 -
100nF 100nF DIG_GREEN DIG_RED DIG_CHROMA DIG_CVBS DIG_LUMA AUX_Y/CVBS 75 55 VIN_9 VIN_12 56 2 75 75 75 75 9 75
Digital encoder inputs
VCR
100nF +12V 10 11 12 13 14
21
VCR_FBLANK
16
17
VCR_CVBS_OUT
GND
14
15
GND
12
13
VCR_RED/C
Digital fast blank
GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA2161R
Notes on operation 1) Supply de-coupling capacitors, 10nF and 10F in parallel should be inserted as close as possible to the supply Pins 14, 15, 24 and 44. When using the dual supply configuration apply the capacitors to Pin 21 in addition to the listed supply pins. 2) For best results with dual supply configuration, two +5V supplies should be used, audio (Pin 24) and video/digital (Pins 14, 44 and 49). 3) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 4) Attention should be given to the electrolytic capacitors on the output pins. In single supply configuration the audio pin dc bias voltage will be approximately 6.0V, therefore the positive terminal of the capacitors should be orientated towards the device pin. 5) To minimise stray capacitance the 75 series resistor on video outputs VOUT_1 to VOUT_6 should be mounted as close as possible to the device Pins 47, 46, 45, 44, 41 and 39. 6) When driving video loads with impedance of 75, video output VOUT_7 (Pin 38) must be connected to the load via a buffer or line driver. This buffer should be located close to the output (Pin 38). 7) In dual supply mode, series protection resistors may be added on Audio outputs which are connected Scart connectors.
- 41 -
CXA2161R
Typical Performance Curves
Video gain - VOUT_1, 2, 3, 4, 5, 6
8 7 6 5 4 3 2 1 0 1 10 Frequency [MHz]
VOUT_1, 2, 3
Gain [dB]
VOUT_4, 5, 6
100
Video gain - VOUT_7
8 7 6 5 4 3 2 1 0 1
Mixer Off
Gain [dB]
Mixer On
10 Frequency [MHz]
100
Audio gain
0.00 Gain [dB] -1.00 -2.00 -3.00 -4.00 1 10 100 Frequency [kHz] 1000 10000
Audio output distortion TV outputs
1 Single supply configuration THD [%] THD [%] 0.1 0.01 0.1 0.01 1
Audio output distortion ROUT1, LOUT1
Single supply configuration
0.001 0.00
1.00
2.00
3.00
0.001 0.00
1.00
2.00
3.00
Input level [Vrms]
Input level [Vrms]
- 42 -
CXA2161R
Package Outline
Unit: mm
56PIN LQFP(PLASTIC)
12.0 0.2 10.0 0.1 42 43 29 28 B 1.7MAX 0.1
A
56 1 + 0.08 0.32 - 0.07 0.65 14
15
0.13 M
0.25 0.1 0.1
+ 0.08 0.32 - 0.07
(11.0)
0.6 0.15
(0.3)
0 to 10
DETAIL A
NOTE: Dimension "" does not include mold protrusion.
(0.5)
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-56P-L01 LQFP056-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.3g
- 43 -
(0.125) + 0.04 0.145 - 0.025
Sony Corporation

▲Up To Search▲

Price & Availability of CXA2161R

	To Download CXA2161R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .